The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of a metal oxide silicon field effect transistor (MOSFET) device.
A field-effect transistor (FETs) can be a semiconductor device fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. FET devices each generally consist of a source, a drain, a gate, and a channel between the source and drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the gate oxide. A voltage applied to the gate across the oxide layer induces a conducting channel between the source and drain, thereby controlling the current flow between the source and the drain. Current integrated circuits often use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-channel and n-channel metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
Group IV semiconductors such as, silicon (Si) and germanium (Ge), are used in conventional CMOS technology. The scaling of the gate length of the MOSFETs have led to faster transistors, circuits, and microprocessors. However, gate length scaling is now facing significant challenges due to high off-state leakage current, increased power consumption, and non-scalability of the operating voltage. The use of low effective mass semiconductor materials, such as many Group III-V compound semiconductors, provide an increase in the maximum obtainable velocity of charge carriers such as electrons and holes.
It is well known that imparting strain to the channel of FETs leads to higher carrier velocities. For example, uniaxial tensile strain leads to higher electron velocity that enhances the performance of n-channel field effect transistors (NFETs) while uniaxial compressive strain leads to higher hole velocity that enhances the performance of p-channel field effect transistors (PFETs). Therefore, MOSFET structures with low effective mass semiconductors and strained channels are highly desired.
Yet another important feature of CMOS technology is that the source and the drain of the FET should not conduct other than through the channel. In conventional Si-based CMOS technology, isolation is achieved using well implants. The well implant method leads to poor isolation in III-V FETs due to low levels of dopant activation that are obtained in III-V semiconductors.